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<title>VPBLENDD — Blend Packed Dwords </title></head>
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<h1>VPBLENDD — Blend Packed Dwords</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 -bit Mode</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>VEX.NDS.128.66.0F3A.W0 02 /r ib</p>
<p>VPBLENDD <em>xmm1, xmm2, xmm3/m128, imm8</em></p></td>
<td>RVMI</td>
<td>V/V</td>
<td>AVX2</td>
<td>Select dwords from <em>xmm2</em> and <em>xmm3/m128</em> from mask specified in <em>imm8</em> and store the values into <em>xmm1</em>.</td></tr>
<tr>
<td>
<p>VEX.NDS.256.66.0F3A.W0 02 /r ib</p>
<p>VPBLENDD <em>ymm1, ymm2, ymm3/m256, imm8</em></p></td>
<td>RVMI</td>
<td>V/V</td>
<td>AVX2</td>
<td>Select dwords from <em>ymm2</em> and <em>ymm3/m256</em> from mask specified in <em>imm8</em> and store the values into <em>ymm1</em>.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RVMI</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv</td>
<td>ModRM:r/m (r)</td>
<td>Imm8</td></tr></table>
<h2>Description</h2>
<p>Dword elements from the source operand (second operand) are conditionally written to the destination operand (first operand) depending on bits in the immediate operand (third operand). The immediate bits (bits 7:0) form a mask that determines whether the corresponding word in the destination is copied from the source. If a bit in the mask, corresponding to a word, is “1", then the word is copied, else the word is unchanged.</p>
<p>VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register are zeroed.</p>
<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register.</p>
<h2>Operation</h2>
<p><strong>VPBLENDD (VEX.256 encoded version)</strong></p>
<pre>IF (imm8[0] == 1) THEN DEST[31:0] (cid:197) SRC2[31:0]
ELSE DEST[31:0] (cid:197) SRC1[31:0]
IF (imm8[1] == 1) THEN DEST[63:32] (cid:197) SRC2[63:32]
ELSE DEST[63:32] (cid:197) SRC1[63:32]
IF (imm8[2] == 1) THEN DEST[95:64] (cid:197) SRC2[95:64]
ELSE DEST[95:64] (cid:197) SRC1[95:64]
IF (imm8[3] == 1) THEN DEST[127:96] (cid:197) SRC2[127:96]
ELSE DEST[127:96] (cid:197) SRC1[127:96]
IF (imm8[4] == 1) THEN DEST[159:128] (cid:197) SRC2[159:128]
ELSE DEST[159:128] (cid:197) SRC1[159:128]
IF (imm8[5] == 1) THEN DEST[191:160] (cid:197) SRC2[191:160]
ELSE DEST[191:160] (cid:197) SRC1[191:160]
IF (imm8[6] == 1) THEN DEST[223:192] (cid:197) SRC2[223:192]
ELSE DEST[223:192] (cid:197) SRC1[223:192]
IF (imm8[7] == 1) THEN DEST[255:224] (cid:197) SRC2[255:224]
ELSE DEST[255:224] (cid:197) SRC1[255:224]</pre>
<p><strong>VPBLENDD (VEX.128 encoded version)</strong></p>
<pre>IF (imm8[0] == 1) THEN DEST[31:0] (cid:197) SRC2[31:0]
ELSE DEST[31:0] (cid:197) SRC1[31:0]
IF (imm8[1] == 1) THEN DEST[63:32] (cid:197) SRC2[63:32]
ELSE DEST[63:32] (cid:197) SRC1[63:32]
IF (imm8[2] == 1) THEN DEST[95:64] (cid:197) SRC2[95:64]
ELSE DEST[95:64] (cid:197) SRC1[95:64]
IF (imm8[3] == 1) THEN DEST[127:96] (cid:197) SRC2[127:96]
ELSE DEST[127:96] (cid:197) SRC1[127:96]
DEST[VLMAX-1:128] (cid:197) 0</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>VPBLENDD:</p>
<p>__m128i _mm_blend_epi32 (__m128i v1, __m128i v2, const int mask)</p>
<p>VPBLENDD:</p>
<p>__m256i _mm256_blend_epi32 (__m256i v1, __m256i v2, const int mask)</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>None</p>
<h2>Other Exceptions</h2>
<p>See Exceptions Type 4; additionally</p>
<table class="exception-table">
<tr>
<td>#UD</td>
<td>If VEX.W = 1.</td></tr></table></body></html>